Lecture 8

Instruction Sets

Information which must be present in an instruction

Operation

Where to get the data

Where to put the result

Where to find the next instruction

In order to put all the information necessary into a single instruction it would have the following format

Opcode	Destination	Source1	Source2	Condition	Next/True	Next/False
Code	Address	Address	Address	Code	Address	Address

Not all instructions need to change the order of instruction execution, so Next/False can be a default: make it the instruction in the memory location after the previous one.

Assume that Next/False is the next sequential instruction

We now need a special storage location inside the CPU (called a register) to store the default address of the next instruction. This register is called the program counter (PC).

Assume most instructions will be sequential

To save space we will split the instruction into two types

Type 1 Instructions: ALU operations

Opcode Destination Source1 Source2

Code Address Address Address

Type 2 Instructions: Control instructions

Opcode Condition Next/True

Code Code Address

Add Flags to the Datapath

The operation and the test of a condition now occur in different instructions. There must now be a way of holding information about the operation. This is usually done by having a special set of single bit storage locations inside the datapath called the flags. The flags are set by some or all ALU operations.

Assume that the destination is often the same as one of the sources.

This is often the case, but where it is not, an extra operation is necessary to move the other source to the destination.

Define a Transfer instruction to move data.

Allow an operand to be a code which represents a temporary location within the datapath.

Add temporary locations called general purpose registers to the datapath.

Registers are usually referred to by a symbolic name e.g. A,B,AX,R1,R2 etc.

Operations may now be from memory to a register (Memory-Register operations), from a register to memory (Register-Memory operations) or from one register to another (Register-Register operations)

Type 1 Instructions: Register-Register ALU operations

Opcode Destination/Source1 Source2

Code Register Register

Type 2 Instructions: Control instructions

Opcode Condition Next/True

Code Code Address

Type 3 Instructions: Memory-Register Transfer instructions

LD Destination Source

Code Register Address

Type 4 Instructions: Register-Memory Transfer instructions

ST Destination Source

Code Address Register

Now lets design a computer from scratch!!

First decide on the instruction set.
Lets have fixed length, 16 bit instructions, 4 general purpose registers and an ALU that performs 5 operations.
This is a list of all the types of instructions.

ADD rd,rs,rt
SUB rd,rs,rt
AND rd,rs,rt
OR rd,rs,rt
XOR rd,rs,rt
LW rd,[rs+imm9]
B dest
BGT dest

ADD rd,rs,imm6
SUB rd,rs,imm6
AND rd,rs,imm6
OR rd,rs,imm6
XOR rd,rs,imm6
SW rd,[rs+imm9]
BE dest
BLT dest

rd is the destination register (except for SW where it is the source) and rs and rt are source registers. imm9 and dest, are signed constants, imm6 is an unsigned constant.

B always branches (realtive to PC+1), BE branches if the zero flag is set, BLT branches if the carry flag is set and BGT branches if carry is clear. The instructions are coded into a 16 bit word as follows (lsb on right).

Possible values for type 0 = ALU    3 reg operands
1 = ALUi   2 regs and an immediate
2 = LW     load word from memory
3 = SW     store word to memory
4 = B      branch
5 = BE     branch if equal
6 = BLT    branch if less than
7 = BGT    branch if greater than type(3) rd(2) rs(2) op(3) rt (2) 0(4)

imm6(6)

imm9(9)

dest(13)

The possible values for op are: 0 = ADD , 1 = SUB, 2 = AND, 3 = OR , 4 = XOR
Now we need some hardware - Here is the logic diagram for a simple machine capable of executing these instructions.

An instruction is executed in 5 stages, Fetch, Decode, Execute, Memory and Write.
The important parts of this diagram to notice are the ALU (Top Centre), the Instruction Register (Bottom Left), The Program Counter (Above and to the right of IR), General Purpose Registers (Centre), Data and Address Busses, Memory, and the Control Unit (Centre Right).

If you would like to see this machine in operation, try the following:

Create a temporary directory on the machine you are using.
Press shift and click here to download the logic simulator (save it in your temporary directory)
Do the same with this (also save it in the temporary directory)
Open a window with your temporary directory in it.
Execute logwin32.exe, and click unzip, this will put the program in the c:\log directory.
Browse the c:\log directory and double click on log.exe.
After the program starts type:

:load cpu

Use the < and > keys to zoom in and out, use the arrow keys to navigate, press 'g' to see the cpu working, magnify the keyboard and click on it to enter data.
Press 'Q' (capital Q), followed by 'y' to exit.

Registers

Program Counter - Holds the address of the next instruction to be executed.
Instruction Register - Holds the instruction being executed.
Memory Address Register - Holds an address to be put onto the address bus.
Memory Data Register - Holds a Word of data going to, or coming from the memory.
General Purpose Registers - Temporarily Hold data for operations. They may also hold addresses.
Flags - Hold information about a previous operation.

The following diagram is for a complete CPU: Fill in the locations of these registers.

Opcode	Destination/Source1	Source2
Code	Register	Register

`Possible values for type` `0 = ALU 3 reg operands` `1 = ALUi 2 regs and an immediate` `2 = LW load word from memory` `3 = SW store word to memory` `4 = B branch` `5 = BE branch if equal` `6 = BLT branch if less than` `7 = BGT branch if greater than`	`type(3)`	`rd(2)`	`rs(2)`	`op(3)`	`rt (2)`	`0(4)`
					`imm6(6)`
				`imm9(9)`
		`dest(13)`