The Controller
The controller is an ASM that implements the instruction set of the computer
When the power is first turned on, and after each instruction has completed the controller:
uses the value in the PC to address memory
the value at that memory location is the next instruction
issues a sequence of signals to the architecture corresponding
to the instruction
The input signals to the controller are:
The current instruction
EQZ
The output signals generated by the controller are:
LDABR load a buffer register
sub subtract instead of add
LDACC load the accumulator
OEACC output enable the accumulator
OECONST output enable the constant
C0/C1 select between constant 0 or 1
OEPC output enable the Program Counter
RESET reset line to gates
LDPC load the PC
INCPC increment the PC
WEMEM write enable memory
OEPORT output enable the I/O port
OEMEM output enable memory
LDMAR load memory address register
DISABLE disables the clock (user re-enables it)
Instruction set
The pico-computer only has 8 instructions:
0 LDA operand Load value at location operand into Acc
1 ADD operand Add value at location operand to Acc
2 SUB operand Subtract value at location operand from Acc
3 STA operand Store value in Acc at location operand
4 JPZ operand If value in Acc is 0 jump to operand
otherwise proceed to next instruction
5 IN Input a number from I/O port
6 CLR Load accumulator with 0
7 HLT Halt the clock
So a set of instructions to input three numbers and add them together is:
5 input number to acc
3 100 store acc to location 100
5 input number to acc
3 101 store acc to location 101
5 input number to acc
1 101 add value from location 101
1 100 add value from location 100
7 Halt
Instructions in detail
For all these instructions we may assume that the PC has already been incremented
0 LDA operand
Algorithm:
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1 Output enable const mux (0) onto bus
Load bus (0) into ABR
2 Load MAR with location of address of operand
3 Load MAR with address of operand
4 Output enable memory
Load Acc with sum of ABR (0) and bus
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1 ADD operand
Algorithm:
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1 Output enable accumulator onto bus
Load bus (accumulator) into ABR
2 Load MAR with location of address of operand
3 Load MAR with address of operand
4 Output enable memory
Load Acc with sum of ABR (accumulator) and bus
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2 SUB operand
Algorithm:
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1 Output enable accumulator onto bus
Load bus (accumulator) into ABR
2 Load MAR with location of address of operand
3 Load MAR with address of operand
4 Output enable memory onto bus
Load Acc with sum of ABR (accumulator) and bus
Subtract line enable |
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3 STA operand
Algorithm:
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1 Load MAR with location of address of operand
2 Load MAR with address of operand
3 Output enable accumulator onto bus
Write-enable memory |
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4 JPZ operand
Algorithm:
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1 Load PC into MAR increment PC in case jump doesn’t occur
2 Output enable memory (operand) onto bus
If EQZ (accumulator contents) enable LDPC to load operand into PC |
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5 IN
Algorithm:
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1 Output enable const mux (0) onto bus
Load bus (0) into ABR
2 Halt the clock
Output enable the I/O port onto the bus
Load the accumulator with the sum of ABR (0) and the value from the I/O port
won’t take effect until user starts clock
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6 CLR
Algorithm:
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1 Output enable const mux (0) onto bus
Load bus (0) into ABR
2 Output enable const mux (0) onto bus
Load the accumulator with the sum of ABR (0) and the value on the bus (0)
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7 HALT
Algorithm:
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1 Disable the clock
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159.233 Lecture 11 -