several flip-flops in a row. One bit is input at one end on each
clock pulse. Each other bit moves one place to the right (or left).
The outputs of each flip-flop are available simultaneously.
can use shift registers for serial to parallel conversion. Input 8
bits on 8 pulses, then read data simultaneously.
Division by 2
can use the above principle to implement a divide by 2 circuit.
the parallel load register (lecture 4) we can use an extra control
determine whether the input to a flip-flop comes from the data lines
or from the previous flip-flop (the left-most flip-flop gets a 0 in
the control line as the address of a 2 input multiplexor, the output
is connected to the input of the flip-flop)
this as an exercise.
your own 2 input mux using AND/OR gates)
Multiplication by 2
can be done by shifting to the left.
powers of two can be done by shifting several times.
extra flip-flop can be added to the ends of the chain.
the case of division by 2, this flip-flop will contain the remainder.
the case of multiplication the flip-flop will flag whether an
overflow has occurred.
74LS75B is a parallel load/shift right register 4 bits wide, which
(with external assistance) can do shift left as well.
Add one to the current number.
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
For the low order bit:
just swap between 0 and 1 - ie it toggles
For higher order bits:
the n’th bit toggles when the n-1’th bit changes from
1 to 0
Use a J-K flip-flop (falling edge triggered) as a toggle.
Use the Qn-1 output as a clock to the Qn flip-flop
This is an ideal case - unfortunately the output of a flip-flop,
like any gate, is slightly delayed with respect to a changing input.
So the toggling of Q1
will be delayed by a few nanoseconds.
only toggle on a change in Q1
so it will be delayed by twice the
This effect will keep on compounding.
These glitches can have quite a disturbing effect.
Consider the case when the counter
is at 0111
At the next pulse we would expect
the counter to show 1000
However because of the delays the following patterns will all
changes but Q1
hasn’t caught up yet
has now changed but Q2
is still to flip over
now has reacted but Q3
is still to change
we get the right answer.
Circuits can be designed so that this ripple effect can be safely
ignored, However it is possible to design a counter that changes all
the gates simultaneously.
We cannot use the preceding bit as a pulse.
The same pulse must be used for each flip-flop.
How do we know when to toggle a flip-flop?
The synchronous counter uses the following fact:
a bit will toggle if all the low-order bits in the previous state
Flip-flops toggle at the same time - but only if J-K’s are
J-K’s are formed by ANDing the output of the previous bits.
Because the new output comes after the toggle by a few
The new state is not involved in any of the inputs
The AND gates are sampling the previous state.
We are deliberately using to our advantage the gate delay time.
Synchronous up-down counter
As an exercise create a synchronous down counter.
(remember that the J-K flip-flop
also has a
Using a control line
we can also create a synchronous up-down counter try it!