This course builds on 59.213 to give you a detailed understanding of the design of computer hardware.
Text and Course Material
Patterson D. and Hennessy J., Computer Organisation and Design: The Hardware/Software Interface, (Morgan Kaufmann 1994)
It is highly recommended that you buy this book.
Lecture Notes and course information is available from http://cs-alb-pc3.massey.ac.nz
The course will be assessed by a combination of practical and theoretical work.
There will be 3 practical assignments and one three hour exam.
The marks for this course will be divided as follows:
Item % of Total Assignments 1-3 30 Final Exam 70
For the assignments, you will be using a logic simulator called "log". The simulator will run in the labs, but you can also take it home. The file you need is on the H drive and is called "loginst.exe". It will run under DOS (not Windows 95). To install, run "loginst.exe" in your root directory. To start the simulator, run"go.bat" in the \log directory (you may have to change some things to get it to run on your hardware).
In the labs, run "lab4.bat" or "lab5.bat" from the H:\LOG directory. The simulator will run a lot faster in lab5!
Documentation for the simulator is available from the web pages and in the file \log\lib\log.doc. All you need to read are the sections "General Information" and "Digital Simulator".
No guarantees are made about how well the software works, I suggest that you save your designs often!
Lectures: 2 lectures per week..
This is a rough plan, the course may not conform to this schedule.
Computing Abstractions and Technology.
How to measure performance, Clock cycle, Cycles per Instruction, Instruction per application, Measurement and Benchmarks, MIPS, MFLOPS
3. Instruction Sets
Operations: Add,Registers, Simplicity - The RISC approach, Register to Register, Memory access, Range and unit addressed, Compilation issues, Machine language, Instruction format, Data format, Designing an ISA, Assemblers, Addressing Modes, Other Instruction set architectures, Evolving ISAs, Classes of architecture
ALUs, Multiplication, Shift and add, Adder trees, Booths algorithm, Division, Repeated subtraction, Reciprocal approximation, Newton iteration, Floating point
5. Datapath and Control
Combinational and sequential logic, Clocks, Program counter, Register file, Single cycle operation with combinational control, Multiple cycle operation with combinational and sequential control, Microprogramming, Data path components, Load and store memory, Branch destination calculation, Memory access, Control unit design, Control Unit operation, Control unit implementation, Multiple cycles per instruction
Execution time model, Ideal speedup, Pipeline overheads, Registers in datapath, Pipeline control, Pipeline control, Hazards and stalls, Forwarding, Branching, Exceptions
7. Memory Hierarchy
Caches, Mappings from memory to cache, Direct mapped cache, Implementation, Cache misses, Write through and write back, Memory access width, Performance issues, Virtual memory, Page replacement, Design considerations, Page tables, TLB, Protection modes, Associative Caches., Set associative
I/O systems, Interfacing I/O to the processor, Bus, Bandwidth, Latency, Variety of I/O devices, Number of I/O devices, Benchmarks, I/O devices, Disc technology, Networks, Implementation of Buses, Bus bottleneck, Bus protocols, Synchronous versus Asynchronous, Increasing bandwidth, Bus arbitration