Microcode

Horizontal Microcode

- control field for each control point in the machine

Vertical Microcode

- compact microinstruction format for each class of microoperation

e.g. 3 classes of microinstruction
branch: µseq-op µadd
execute: ALU-op A,B,R
memory: mem-op S, D

microcode looks  like RISC code.

Extreme Horizontal

Depending on bus organization, many potential control combinations are not possible. e.g. put 2 regs on a bus at the same time.
Makes sense to encode fields to save ROM space

Encoded in a field which is decoded rather than lots of separate bits

NOTE: encoding should be just sufficient that parallel actions that the datapath should still be specifiable in a single microinstruction
 

Horizontal

Gives more control over the potential parallelism of operations in the datapath
But uses up lots of control store

Vertical

Easier to program, not very different from programming a RISC machine in assembly language
But extra level of decoding may slow the machine down
 

Pros and cons of microprogramming

But

Designing a Microinstruction Set for our MIPS subset.

Start with list of control signals
Group signals together that make sense: called "fields"
Place fields in some logical order (ALU operation & ALU operands first and microinstruction sequencing last)
Create a symbolic legend for the microinstruction format, showing name of field values and how they set the control signals
To minimize the width, encode operations that will never be used at the same time

Signal name   Effect when 0                Effect when 1
ALUSelA       1st ALU operand = PC         1st ALU operand = Reg[rs]
RegWrite      None                         Reg. is written
MemtoReg      Reg. write data input = ALU  Reg. write data input = memory
RegDst        Reg. dest. no. = rt          Reg. dest. no. = rd
TargetWrite   None                         Target reg. = ALU
MemRead       None                         Memory at address is read
MemWrite      None                         Memory at address is written
IorD          Memory address = PC          Memory address = ALU
IRWrite       None                         IR = Memory
PCWrite       None                         PC = PCSource
PCWriteCond   None                         IF ALUzero then PC = PCSource

Signal name Value Effect
ALUOp       00    ALU adds
            01    ALU subtracts
            10    ALU does function code
            11    ALU does logical OR
ALUSelB     000   2nd ALU input = Reg[rt]
            001   2nd ALU input = 4
            010   2nd ALU input = sign extended IR[15-0]
            011   2nd ALU input = sign extended, shift left 2 IR[15-0]
            100   2nd ALU input = zero extended IR[15-0]
PCSource    00    PC = ALU
            01    PC = Target
            10    PC = PC+4[29-26] : IR[25-0] << 2

For next state function (next microinstruction address),
use Sequencer-based control unit from last lecture

Signal   Value Effect
Sequen   00    Next µaddress = 0
-cing    01    Next µaddress = dispatch ROM 1
         10    Next µaddress = dispatch ROM 2
         11    Next µaddress = µaddress + 1

Field Name       Width Control Signals Set
ALU Control      2     ALUOp
SRC1             1     ALUSelA
SRC2             3     ALUSelB
ALU Destination  4     RegWrite, MemtoReg, RegDst, TargetWrite
Memory           3     MemRead, MemWrite, IorD
Memory Register  1     IRWrite
PCWrite Control  4     PCWrite, PCWriteCond, PCSource
Sequencing       2     AddrCtl

Total 20

Field Name    Values for Field       Function of Field with Specific Value
ALU           Add                    ALU adds
              Subt.                  ALU subtracts
              Func code              ALU does function code
              Or                     ALU does logical OR
SRC1          PC                     1st ALU input = PC
              rs                     1st ALU input = Reg[rs]
SRC2          4                      2nd ALU input = 4
              Extend                 2nd ALU input = sign ext. IR[15-0
              Extend0                2nd ALU input = zero ext. IR[15-0]
              Extshft                2nd ALU input = sign ex., sl IR[15-0]
              rt                     2nd ALU input = Reg[rt]
ALU dest      Target                 Target = ALU
              rd                     Reg[rd] = ALU
Memory        Read PC                Read memory using PC
              Read ALU               Read memory using ALU output
              Write ALU              Write memory using ALU output
Memory reg    IR                     IR = Mem
              Write rt               Reg[rt] = Mem
              Read rt                Mem = Reg[rt]
PC write      ALU                    PC = ALU output
              Target-cond.           IF ALU Zero then PC = Target
              jump addr.             PC = PCSource
Sequencing    Seq                    Go to sequential µinstruction
              Fetch                  Go to the first microinstruction
              Dispatch i             Dispatch using ROMi (1 or 2).
 
Label ALU  SRC1 SRC2 ALU Dest. Memory Mem. Reg.  PC Write  Sequencing
Fetch Add PC 4   Read PC IR ALU Seq
  Add PC Extshft Target       Dispatch 1
LWSW1 Add rs Extend         Dispatch 2
LW2 Add rs Extend   Read ALU     Seq
  Add rs Extend   Read ALU Write rt   Fetch
SW2 Add rs Extend   Write ALU Read rt   Fetch
                 
Rtype Func rs rt         Seq
  Func rs rt rd       Fetch
BEQ1 Subt. rs rt       Target- cond. Fetch
JUMP1             jump address Fetch
ORI Or rs Extend0          Seq
  Or rs Extend0  rd       Fetch