THE FET7 MOS Models in Analog

This release features a new family of MOS models, the FET7 series (three-terminal gates PFET7T and NFET7T, and four-terminal gates PFET7F and NFET7F) as well as several supporting gates. These models are different from previous MOS models in analog, in structure as well as form. This Web page is a quick introduction to these models; for complete details, see this paper [Postscript, 300 KByte compressed] [Adobe PDF, 680 KByte, requires Acroread 3.0].

The model on which these gates are based is parameterized in a new way. The parameters are properties of the physical construction of devices. In addition, they are independent properties. Therefore, it makes sense to vary one parameter while the others are left fixed. This is useful in terms of finding values which give a good fit to a given process, and also as a way of exploring the effect of process values on device and circuit behavior.

The simulator has been modified so that the simulation environment itself holds information about MOS physics and fabrication; in previous models, each gate held this information redundantly. This information has been broken up into several categories:

At start-up, the simulator reads in the default parameters for the FET7 series from the file log/lib/mos.cnf. The default mos.cnf file contains parameter values suitable for the MOSIS SCN 1.2u process (SCN12, fab run N52V); this file also appears as mosscn12.cnf. Parameter files for the HP CMOS26G 0.8um process (mos26g.cnf) and the HP CMOS14TB 0.5um process (mos14tb.cnf) are also supplied.

The annotated file mos_example.cnf explains the process of converting MOSIS-supplied documentation for a process to a cnf file. We hope users will create cnf files for other processes, and send them along to us for inclusion in later releases.

The LOGSPC utility for creating Spice files from Log schematics has been updated to be FET7-aware. See the file log/lib/spctest.lgf for an example of using FET7 transistors for SPICE-deck creation.

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