Ingo Cyliax (cyliax@cs.indiana.edu) has developed several tools to support Diglog as a schematic capture environment for Xilinx FPGA chips. He maintains these tools, and hosts them at an FTP site at Indiana University. Click on the links below to retreive source files from that FTP site.

XNF netlist generation
This tool converts NTK netlist files, generated by Diglog, into XNF netlists.
Sample designs
Several sample designs for using Diglog to create Xilinx netlists.

Note that in order to create complete designs, you will still need to have access to the Xilinx core FPGA tools. The entry level pacakage of just the core tools which can target the smaller Xilinx chips (up to 3042 and 4003) is available for $1000 from several chip suppliers. Chipmunk and this pacakage is an inexpensive way to program Xilinx FPGAs.

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UC Berkeley / CS Division / 387 Soda Hall / Berkeley CA 94720